With recent advancement of digital technologies, higher functionality of electronic hardware such as portable information devices and home information appliances have been brought out. For this reason, demands for an increase in a capacity of a nonvolatile memory element, a reduction in writing electric power, a reduction in write/read-out time, and longer life have been increasing.
In response to such demands, it is said that there is a limitation on miniaturization of an existing flash memory using a floating gate. On the other hand, a nonvolatile memory element (resistance variable memory) using a variable resistance layer as a material of a memory portion is attainable with a simple structure. Therefore, further minitualization, a higher-speed, and further electric power saving of the nonvolatile memory element are expected.
When using the variable resistance layer as the material of the memory portion, its resistance value varies from a high-resistance value to a low-resistance value or from the low-resistance value to the high-resistance value, for example, by inputting electric pulses. In this case, it is necessary to clearly distinguish two values, i.e., the high-resistance value and the low-resistance value, to vary the resistance value stably between the low-resistance value and the high-resistance value at a high-speed, and to hold these two values in a nonvolatile manner. For the purpose of stabilization of such a memory property and minitualization of memory elements, a variety of proposals have been proposed in the past.
As one of such proposals, patent document 1 discloses a memory element in which memory cells are formed by resistance variable elements each of which includes two electrodes and a storing layer sandwiched between these electrodes and is configured to reversibly vary a resistance value of the storing layer. FIG. 27 is a cross-sectional view showing a configuration of such a conventional memory element.
As shown in FIG. 27, the memory element has a configuration in which a plurality of resistance variable elements 10 forming memory cells are arranged in array. The resistance variable element 10 has a configuration in which a high-resistance film 2 and an ion source layer 3 are sandwiched between a second electrode 1 and a first electrode 4. The high-resistance film 2 and the ion source layer 3 form a storing layer. The storing layer enables data to be stored in the resistance variable element 10 in each memory cell.
The resistance variable elements 10 are disposed above MOS transistors 18 formed on a semiconductor substrate 11. The MOS transistor 18 includes source/drain regions 13 formed in a region separated by an element separating layer 12 inside the semiconductor substrate 11 and a gate electrode 14. The gate electrode 14 also serves as a word line which is one address wire of the memory element.
One of the source/drain regions 13 of the MOS transistor 18 is electrically connected to the second electrode 1 of the resistance variable element 10 via a plug layer 15, a metal wire layer 16, and a plug layer 17. The other of the source/drain regions 13 of the MOS transistor 18 is connected to the metal wire layer 16 via the plug layer 15. The metal wire layer 16 is connected to a bit line which is the other address wire of the memory element.
By applying electric potentials of different polarities between the second electrode 1 and the first electrode 4 of the resistance variable element 10 configured as described above, ion source of the ion source layer 3 forming the storing layer is caused to migrate to the high-resistance layer 2. Or, the ion source is caused to migrate from the high-resistance layer 2 to the first electrode 4. Thereby, the resistance value of the resistance variable element 10 transitions from a value of a high-resistance state to a value of a low-resistance state, or from a value of the low-resistance state to a value of the high-resistance state, so that data is stored.
A memory element (phase-change type memory) is also known, in which a variable resistance material sandwiched between a first electrode and a second electrode forms a first electric pulse varying resistance layer having a polycrystalline structure and a second electric pulse varying resistance layer having a nano crystal or an amorphous structure. The resistance layer formed of the variable resistance material is controlled so that its resistance value is caused to vary according to a voltage and a pulse width of electric pulses applied, thereby operating as a resistance variable element (see, for example, patent document 2).
A perovskite material (e.g., Pr(1-x)CaXMnO3(PCMO), LaSrMnO3 (LSMO), GdBaCoXOY (GBCO) or the like) may be used as the variable resistance material of the nonvolatile memory element, because its resistance value varies according to electric pulses applied (patent document 3). In this nonvolatile memory element, a predetermined electric pulse is applied to the perovskite material to increase or decrease its resistance value, and different numeric values are stored according to the resulting varying resistance values. PCMO is writable with electric pulses having a pulse width of 100 nsec or smaller and is therefore expected to operate as a high-speed nonvolatile memory element (non-patent document 1).
However, the perovskite material has a complex composition and is not always compatible with a CMOS process. As a configuration suitable for the CMOS process, a nonvolatile memory element using as the variable resistance material a transition metal oxide (Ni—O, Ti—O, Hf—O, Zr—O) having a simple composition has been proposed (non-patent document 2). Patent document 4 discloses as the variable resistance material, NiO, V2O5, ZnO, Nb2O5, TiO2, WO3, or CoO. These materials consist of two elements and therefore, composition control therefor and film forming using them are relatively easy. In addition, these materials may have relatively high affinity with a semiconductor manufacturing process.
Patent document 5 discloses a variety of variable resistance materials obtained by rapid metal-insulator transfer of a p-type oxide semiconductor material comprising metal elements including tantalum. In particular, specific examples thereof are Ga, As and V O2. Patent documents 6 and 7 disclose, as examples of a variable resistance material, titanium oxide and Ta2O5 which is tantalum oxide as insulators whose resistance states change, respectively.
As used herein, an electric pulse for changing the element from the high-resistance state to the low-resistance state is referred to as a low-resistance state attaining pulse, and an electric pulse for changing the element from the low-resistance state to the high-resistance state is referred to as a high-resistance state attaining pulse.
Desirably, the resistance value of the resistance variable memory element in the low-resistance state does not vary even when the low-resistance state attaining pulse is applied thereto. However, a problem arises, in which, when amorphous rare earth metal is used as the variable resistance material, the resistance value of the resistance variable memory element in the low-resistance state varies if the low-resistance attaining pulse is applied thereto. To solve such a problem, patent document 7 discloses a configuration for connecting an electric load to the variable resistance memory element.
Control is easily executed when the difference (switching window) in voltage between the low-resistance state attaining pulse and the high-resistance state attaining pulse is larger. Patent document 8 discloses that a resistor portion is provided in a resistance variable memory element so that the difference in voltage between the low-resistance state attaining pulse and the high-resistance state attaining pulse is made larger.    Patent document 1: Japanese Laid-Open Patent Application Publication No. 2006-40946    Patent document 2: Japanese Laid-Open Patent Application Publication No. 2004-349689    Patent document 3: U.S. Pat. No. 6,204,139 Specification    Patent document 4: Japanese Laid-Open Patent Application Publication No. 2004-363604    Patent document 5: Japanese Laid-Open Patent Application Publication No. 2006-32898    Patent document 6: Japanese Laid-Open Patent Application Publication No. Hei. 7-263647    Patent document 7: Japanese Laid-Open Patent Application Publication No. 2005-216387    Patent document 8: Japanese Laid-Open Patent Application Publication No. 2006-229227    Non-patent document 1: Zuang, W. W. et al., 2002, “Novell Colossal Magnetoresistive Thin Film Nonvolatile Resistance Random Access Memory (RRAM)”, IEDM Technical Digest    Non-patent document 2: Baek, J. G. et al., 2005, “Multi-layer Cross-point Binary Oxide Resistive Memory (OxRRAM) for Post-NAND Storage Application”, IEDM Technical Digest    Non-patent document 3 Baek, J. G. et al., 2004, “Highly Scalable Non-volatile Resistive Memory using Simple Binary Oxide Driven by Asymmetric Unipolar Voltage Pulses”, IEDM Technical Digest, pp. 587-590    Non-patent document 4 Japanese Journal of Applied Physics, vol. 45, no. 11, 2006, pp. L310-L312, FIG. 2